EDN

Hardware Emulation in Mid-Life — Moving to Center Stage

This is part 2 of a 3-part series called, Hardware Emulation: Realizing its Potential. This is part 2 of a 3-part series called, Hardware Emulation: Realizing its Potential. Approaching the new ...
Semiconductor Engineering

Pushing The Limits Of Hardware-Assisted Verification

As semiconductor complexity continues to escalate, so does the reliance on hardware-assisted simulation, emulation, and prototyping. Since chip design first began, engineers have complained their ...
EDN

Verifying large models in RTL simulation

Verifying that a multi-million gate ASIC will function according to its specification prior to being built into a system composed of hundreds or thousands of additional ASICs plus thousands of other ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Semiconductor Engineering

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero ...