Plano, Texas, USA -- September 24, 2024-- Siemens Digital Industries Software today announced that Japan-based Preferred ...

Certus is excited to announce that its 1.2V/3.3V wire-bond I/O library in TowerJazz’s 65nm process is silicon-verified, and ...

Incorporating BroadR-Reach™ technology for Automotive Excellence, this PHY delivers exceptional performance for automotive and industrial applications, providing a superior alternative to traditional ...

At our recent SiFive Day event, SiFive’s CEO Patrick Little explained that “AI and RISC-V were made for each other.” The open RISC-V standard frees ...

Silvaco today announced that its 2024 TCAD Baseline Release simulation platform with digital twin modeling, provides support for planar CMOS, FinFET and Gate-All-Around (GAA) transistor technologies, ...

Dolphin Design, the leader in Power management IP, and SigmaSense, the leader in direct-to-digital precision sensing, today ...

Global Unichip Corp. (GUC), the Advanced ASIC Leader, is pleased to announce that its 3nm HBM3E Controller and PHY IP have ...

Comcores and EXTOLL have successfully performed the interoperability test of Comcores JESD204C IP with Extoll PHY.

Partnership enables AI developers to train, optimize and deploy embedded ML models on the Ceva-NeuPro-Nano NPU IP, pre-silicon, via Edge Impulse Platform ...

As technology continues to evolve at a rapid pace, the importance of robust and efficient interconnect standards cannot be overstated. Peripheral Component ...

JESD319: JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®) defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ...

XtremeSilica has marked a major milestone with the successful shipment of its first SDRAM Controller for Tapeout GF40nm.